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this document is a general product descript ion and is subject to change without notice. hynix does not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev 0.2 / apr. 2008 1 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash 16gb nand flash H27UAG8T2M http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 2 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash document title 16gbit (2gx8bit) nand flash memory revision history revision no. history draft date remark 0.0 initial draft. feb. 18. 2008 preliminary 0.1 1) add ulga package - figures & text are added. mar. 27. 2008 preliminary 0.2 1) add the text relating to the multi-plane copyback function - multi-plane copyback function must be used in the block which has been programmed with multi-plane page program. 2) correct the ball config uration of the lga package. apr. 14. 2008 preliminary http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 3 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash features summary high density nand flash memories - cost effective solutions for mass storage applications multi-plane architecture - array is split into two independent planes. parallel operations on both planes are available, halving program, read and erase time. nand interface - x8 bus width - multiplexed address/ data - pinout compatibility for all densities supply voltage -3.3v device : vcc = 2.7 v ~3.6 v memory cell array - (4k + 128 ) bytes x 128 pages x 4096 blocks page size - x8 device : (4096+128 spare) bytes : H27UAG8T2M block size - x8 device : (512k+16k) bytes page read / program - random access: 60us (max) - sequential access: 25ns (min) - page program time: 800us (typ) - multi-plane page program time : 800us (typ) copy back program -fast page copy fast block erase - block erase time: 2.5ms (typ) - multi-plane block erase time (2blocks) : 2.5ms(typ) status register electronic signature - 1st cycle: manufacturer code - 2nd cycle: device code - 3rd cycle: internal chip number, cell type, number of simultaneously programmed pages. - 4th cycle: page size, block size, organization, spare size - 5th cycle: multi-plane information chip enable don?t care -simple interface with microcontroller hardware data protection - program/erase locked during power transitions. data retention - 10k program / erase cycles (with 4bit/512byte ecc) - 10 years data retention package - H27UAG8T2Mtr : 48-pin tsop1(12 x 20 x 1.2 mm) - H27UAG8T2Mtr (lead & halogen free) - H27UAG8T2Mur : 52-ulga (12 x 17 x 0.65 mm) - H27UAG8T2Mur (lead & halogen free) http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 4 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash 1.summary description the H27UAG8T2M is a 2048mx8bit with spare 64mx8 bit capacity . the device is offered in 3.3v vcc core power supply, 3.3v input-output power supply. its nand cell provides th e most cost-effective solution for the solid state mass stor - age market. the memory is divided into blocks that can be er ased independently so it is po ssible to preserve valid data while old data is erased. the device contains 4096 blocks, composed by 128 pages cons isting in two nand structures of 32 series connected flash cells. every cell holds two bits. like all other 4kb page nand flash devices, a program operation allows to write the 4224-byte page in typical 800us and an erase operation can be performed in typical 2.5ms on a 512k-byte block. in addition to this, thanks to multi-plane architecture, it is possible to pr ogram 2 pages a time (one per each plane) or to read 2 pages a time (one per each plane) to erase 2 bl ocks a time (again, one per each plane). as a consequence, multi-plane architecture allows program ti me reduction and erase time reduction. data in the page can be read out at 25ns cycle time per byte. the i/o pins serve as the ports for address and data input/output as well as command input. this interface allows a reduced pin count and easy migrat ion towards different densities, without any rearrangement of footprint. commands, data and addresses are synchr onously introduced using ce, we, ale and cle input pin. the on-chip program/erase controller automates all read, program and erase functions including pulse repetition, where required, and internal verification and margining of data. the modify op erations can be locked using the wp input. the output pin r/b (open drain buffer) signals th e status of the device during each operation. in a system with multiple me mories the r/b pins can be connected all to gether to provide a global status signal. even the write-intensive systems can take advantage of the H27UAG8T2M extended reliability of 10k program/erase cycles by providing ecc (error correcting co de) with real time mapping-out algorithm. the chip supports ce don?t care function . this function allows the direct down load of the code from the nand flash memory device by a microcontroller, since the ce transitions do not stop the read operation. this device includes also extra features like otp/unique id area. the H27UAG8T2M series are available in 48 - tsop1 12 x 20 mm, 52 - ulga 12 x 17 mm package. 1.1 product list part number organization vcc range package H27UAG8T2M x8 2.7~3.6 volt 48-tsop1, 52-ulga http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 5 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash 9&& 966 :3 &/( $/( 5( :( &( ,2a,2 5% figure 1: logic diagram io7 - io0 data input / outputs cle command latch enable ale address latch enable ce chip enable re read enable we write enable wp write protect r/b ready / busy vcc power supply vss ground nc no connection table 1: signal names 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9ff 9vv 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 1& 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 9fft 9vvt 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 1& 1$1')odvk 7623 [ figure 2. 48tsop1 contact, x8 device http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 6 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash nc nc nc nc nc nc nc nc nc nc nc nc /we /wp vss io0 io1 io2 io6 io7 io5 io4 vss io3 r/b nc nc nc nc nc nc nc nc nc vss vss vcc vcc nc cle ale /ce /re nc nc nc nc nc nc nc nc nc a b c d e f g h j k l m n 12 345 6 7 0 8 oa ob oc od oe of figure 3. 52-ulga contact, x8 device (top view through package) http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 7 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash 1.2 pin description pin name description io0-io7 data inputs/outputs the io pins allow to input comma nd, address and data and to output data during read / program operations. the inputs are latched on the rising edge of write enable (we ). the i/o buffer float to high-z when the device is deselected or the outputs are disabled. cle command latch enable this input activates the latching of the io inputs inside the command register on the rising edge of write enable (we ). ale address latch enable this input activates the latching of the io inputs inside the address register on the rising edge of write enable (we ). ce chip enable this input controls the selection of the device. we write enable this input acts as clock to latch command, address and data. the io inputs are latched on the rise edge of we . re read enable the re input is the serial data-out control, and when ac tive drives the data onto the i/o bus. data is valid trea after the falling edge of re which also increments the inte rnal column address counter by one. wp write protect the wp pin, when low, provides an hardware protecti on against undesired modify (program / erase) operations. r/b ready busy the ready/busy output is an open drain pin that signals the state of the memory. vcc supply voltage the vcc supplies the power for all th e operations (read, write, erase). vss ground nc no connection table 2: pin description note: 1. a 0.1uf capacitor should be connected between the vc c supply voltage pin and the vss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations. http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 8 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash 0 plane 4k bytes 128 bytes i/o0 ~ 7 1 page = (4k+128)bytes 1 block = (4k+128)bytes x 128pages = (512k+16k)bytes 1 device = (512k+16k)byte x 4096block = 16,896 mbit page buffer 2048 blocks per plane (4096 blocks per device) 1 3 4092 4093 4094 4095 2 0 1 plane . . . . . . figure 4: array organization io0 io1 io2 io3 io4 io5 io6 io7 1st cycle a0 a1 a2 a3 a4 a5 a6 a7 2nd cycle a8 a9 a10 a11 a12 l (1) l (1) l (1) 3rd cycle a13 a14 a15 a16 a17 a18 a19 a20 4th cycle a21 a22 a23 a24 a25 a26 a27 a28 5th cycle a29 a30 a31 l (1) l (1) l (1) l (1) l (1) table 3: address cycle map(x8) note: 1. l must be set to low. 2. 1st & 2nd cycle are column address. 3. 3rd to 5th cycle are row address. http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 9 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash function 1st cycle 2nd cycle 3rd cycle 4th cycle acceptable command during busy page read 00h 30h - - read for copy-back 00h 35h - - read id 90h - - - reset ffh - - - yes page program 80h 10h - multi-plane page program 80h 11h 81h 10h multi-plane read 60h 60h 30h - copy back program 85h 10h - - multi-plane copyback program 85h 11h 81h 10h multi-plane copyback read 60h 60h 35h - block erase 60h d0h - - multi-plane block erase 60h 60h d0h - read status register 70h - - - yes random data input 85h - - - random data output 05h e0h - - multi plane random data output 00h 05h e0h - page program with backward compatibility (2kb) 80h 11h 80h 10h copy back program with backward compatibility (2kb) 85h 11h 85h 10h table 4: command set cle ale ce we re wp mode h l l rising h x read mode command input l h l rising h x address input(5 cycles) h l l rising h h write mode command input l h l rising h h address input(5 cycles) lllrisinghhdata input l l l h falling x data output l l l h h x during read (busy) x x x x x h during program (busy) x x x x x h during erase (busy) xxxxxlwrite protect xxhxx0v/vccstand by table 5: mode selection http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 10 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash 2. bus operation there are six standard bus operations that control the devi ce. these are command input, address input, data input, data output, write protect, and standby. typically glitches less than 3 ns on chip enable, write enab le and read enable are ignored by the memory and do not affect bus operations. 2.1 command input. command input bus operation is used to give a command to the memory device. command are accepted with chip enable low, command latch enable high, address latch enab le low and read enable high and latched on the rising edge of write enable. moreover for commands that starts a modifying operation (write/erase) the write protect pin must be high. see figure 6 and table 12 for details of the timings requirements. comm and codes are always applied on io7:0, disregarding the bus configuration. 2.2 address input. address input bus operation allows the inse rtion of the memory address. five cycl es are required to input the addresses for the 16gbit devices. addresses are accepted with chip enable low, address latch enable high, command latch enable low and read enable high and latched on the rising edge of write enable. moreover for commands that starts a modifying operation (write/erase) the writ e protect pin must be high . see figure 7 and table 12 for details of the timings requirements. addresses are always applied on io(7:0), disregarding the bus configuration. in addition, addresses over the addressable space are disregar ded even if the user sets them during command insertion. 2.3 data input. data input bus operation allows to feed to the device the data to be programme d. the data insertion is serially and timed by the write enable cycles. data are accepted only with chip enable low, address latch enable low, command latch enable low, read enable high, and write protect high and latched on the rising edge of write enable. see figure 8 and table 12 for details of the timings requirements. 2.4 data output. data output bus operation allows to read data from the memory array and to check the status register content, the id data. data can be serially shifted out to ggling the read enable pin with chip enable low, write enable high, address latch enable low, and command latch enable low. see figu res 8,9,10,11,12,13 and table 12 for details of the timings requirements. 2.5 write protect. hardware write protection is activated when the write protec t pin is low. in this condition modify operation does not start and the content of the memory is not altered. write prot ect pin is not latched by write enable to ensure the protec - tion even during the power up phases. 2.6 standby in standby mode the device is deselected, outputs are disabl ed and power consumption is reduced. stand-by is obtained holding high, at least for 10us, ce pin. http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 11 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash 3. device operation 3.1 page read. page read operation is initiated by writing 00h and 30h to the command register along with five address cycles. in two consecutive read operaions, the second one need 00h command, which five address cycles and 30h command initiates that operation. two types of operations are available: random read, serial page read. the random read mode is enabled when the page address is changed. the 4224 bytes of data within the se lected page are transfered to the data registers in less than 60us(tr). the system controller may de tect the completion of this data tran sfer 60us(tr) by analyzing the output of r/ b pin. once the data in a page is lo aded into the data registers, they ma y be read out in 25ns cycle time by sequentially pulsing re . the repetitive high to low transitions of the re clock make the device ou tput the data starting from the selected column address up to the last column address. the device may output random data in a page instead of the consecutive sequential data by writing random data output command. the column address of next data, which is going to be out, may be changed to the address which follows random data output command. random data output can be operated multiple times re gardless of how many times it is done in a page. 3.2 multi-plane page read multi-plane page read is an extension of page read, for a si ngle plane with 4,224 byte page registers. since the device is equipped with two memory planes, activating the two sets of 4,224 byte page registers enables a random read of two pages. multi-plane page read is initiated by repeatin g command 60h followed by three address cycles twice. in this case only same page of same block can be selected from each plane. after read confirm command(30h) the 8,448 bytes of data with in the selected two page are transferred to the data registers in less than 60us(tr). the system controller can detect the completion of data transfer(tr) by monitoring the output of r/ b pin. once the data is loaded into the data registers, the data output of first plan e can be read out by issuing command 00h with five address cycles, command 05h with two column address and finally e0 h. the data output of second plane can be read out using the identical comma nd sequences. the restrictions for mu lti-plane page read are shown in fig - ure 15. multi-plane read must be used in the block wh ich has been programmed with multi-plane page program. http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 12 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash 3.3 page program. the device is programmed by page. the number of consec utive partial page programming operation within the same page without an intervening er ase operation must not exceed 1 times. the addressing should be done on each pages in a block. a page program cycle consists of a serial data loading period in which up to 4224bytes of data may be loaded into the data register, followe d by a non-volatile programming period where the loaded data is programmed into the appropriate cell. the serial da ta loading period begins by inputting the serial data in put command (80h), followed by the five cycle address inpu ts and then serial data. the bytes othe r than those to be programmed do not need to be loaded. the device suppo rts random data input in a page. the column address of next data, which will be entered, may be changed to the address which follows random data input command (85h). random data input may be operated multiple times regardless of how many times it is done in a page. the page program confirm command (10h) initia tes the programming process. writing 10h alone without previously entering the serial data will not initiate the programming process. th e internal write state controller auto- matically executes the algorithms and timings necessary for program and verify, thereby freeing the system control- ler for other tasks. once the program process starts, the re ad status register command may be entered to read the status register. the system controller can detect the completion of a program cycle by monitoring the r/b output, or the status bit (i/o 6) of the status register. only the read status command and reset command are valid while pro- gramming is in progress. when the page program is comp lete, the write status bit (i /o 0) may be checked. the internal write verify detects only errors for "1 "s that are not successfully programmed to "0"s. the command register remains in read status command mode until another valid command is written to the com- mand register. figure 16 details the sequence. 3.4 multi-plane program. device supports multiple plane program: it is possibl e to program in parallel 2 pages, one per each plane. a multiple plane program cycle consists of a double serial data loadin g period in which up to 4224bytes of data may be loaded into the data register, foll owed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. the serial data loading period begins by inputting the serial data input command (80h), followed by the five cycle address inputs and then serial da ta for the 1st page. address for this page must be within 1st plane (a<20>=0). the data of 1st pa ge other than those to be programmed do not need to be loaded. the device supports random data input exactly like page program operation. the dummy page program confirm command (11h) stops 1st page data input and the device becomes busy for a short time (tdbsy). once it has become ready again, 81h command must be issued, followed by 2nd page address (5 cycles) and its seri al data input. address for this page must be within 2nd plane (a<20>=1). program confirm co mmand (10h) makes parallel programming of both pages start. user can check operation status by r/b pin or read status register command, as if it were a normal page pro- gram; status register command is also av ailable during dummy busy time (tdbsy). in case of fail in 1st or 2nd page program, fail bit of status register will be set: device supports pass/fail status of each plane. (io0 : total, io1: plane0, io2: plane1). figure 18 details the sequence. http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 13 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash 3.5 block erase. the erase operation is done on a block basis. block address loading is accomplished in th ere cycles initiated by an erase setup command (60h). only address a20 to a31 is va lid while a13 to a19 is ignored. the erase confirm com - mand (d0h) following the block address lo ading initiates the internal erasing proc ess. this two step sequence of setup followed by execution command ensures th at memory contents are not accidental ly erased due to external noise con - ditions. at the rising edge of we after the erase confirm command input, the internal write controller handles erase and erase verify. once the erase process starts, the read status register command may be entered to read the status register. the system controller can detect the completion of an erase by monitoring the r/b output, or the status bit (i/o 6) of the status register. only the read status command and re set command are valid while erasing is in progress. when the erase operation is completed, the writ e status bit (i/o 0) may be checked. figure 19 details the sequence. 3.6 multi-plane erase. multiple plane erase, allows parallel eras e of two blocks, one per each memory plane. block erase setup command (60h) must be repeated two times, each time followed by 1s t block and 2nd block address respectively (3 cycles each). as for block erase, d0h command makes embedded operat ion start. multi-plane erase does not need any dummy busy time be tween 1st and 2nd block address insertio n. address limitation required for multiple plane program applies also to mu ltiple plane erase, as well as operation progress can be checked like for mul - tiple plane program. figure 20 details the sequence 3.7 copy-back program copy-back program with read for copy-back is configured to quickly and efficiently rewrite data stored in one page without data reloading when the bit error is not in data stored. since the time-consu ming re-loading cycles are removed, the system performance is improved. the benefit is especially obvious when a po rtion of a block is updated and the rest of the block also needs to be copied to the newly assigned free bl ock. copy-back operation is a sequential execution of read for copy-back and of copy-back program wi th the destination page addr ess. a read operation with "35h" command and the address of the source page moves th e whole 4224-byte data into the internal data buffer. a bit error is checked by sequential reading the data output. in the case where there is no bit error, the data do not need to be reloaded. therefore copy-back program operation is initiated by issuing page-copy data-input command (80h) with destination page address. actual programming operat ion begins after program confirm command (15h) is issued. once the program process starts, the read status register command (70h) may be entered to read the status register. the system controller can detect the completion of a progra m cycle by monitoring the r/b output, or the status bit(i/ o 6) of the status register. when the copy-back program is complete, the write status bit(i/o 0) may be checked(figure 21 & figure 22). the command register remains in read status command mode until another valid command is written to the command register. during copy-back program, data modification is possible using random data input command (85h) as shown in figure 21. copy-back program operation is allowed only within same plane. http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 14 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash 3.8 multi-plane copy-back program multi-plane copy-back program is an extension of copy-bac k program, for a single plane with 4224 byte page regis - ters. since the device is equipped with two memory planes, activating the two sets of 4224 byte page registers enables a simultaneous programming of two pages. figure 23 shows the command sequence for the multi-plane copy- back operation. multi-plane copyback fu nction must be used in the block whic h has been programmed with multi-plane page program. 3.9 read status register. the device contains a status register which may be read to find out whether, program or erase operation is com - pleted, and whether the program or eras e operation is completed successfully. after writing 70h command to the com - mand register, a read cycle outputs th e content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/ b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 13 for specific status register definitions. the command register remains in status read mode until further commands are issued to it. therefore, if the status register is read during a random read cycle, the read command (00h) should be given before starting read cycles. 3.10 read id. the device contains a product identification mode, initiate d by writing 90h to the command register, followed by an address input of 00h. five read cycles sequentially output the ma nufacturer code (adh), and the device code and 3rd, 4th, 5th cycle id, respectively. the command register remain s in read id mode until further commands are issued to it. figure 25 shows the operation sequence, while tables 15 explain the byte meaning. 3.11 reset. the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during random read, program or erase mode, the reset operat ion will abort these operatio ns. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, an d the status register is cleared to valu e e0h when wp is high. refer to table 13 for device status after reset operation. if the device is already in reset state a new reset command will not be accepted by the command register. the r/ b pin goes low for trst after the reset command is written. refer to figure 28. http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 15 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash 4. other features 4.1 data protection & power on/off sequence the device is designed to offer protection from any involu ntary program/erase during powe r-transitions. an internal voltage detector disables all functions when ever vcc is below about 2.0v(3.3v device). wp pin provides hardware pro - tection and is recommended to be kept at vil during power-up an d power-down. a recovery time of minimum 10us is required before internal circuit gets ready for any command sequences as shown in figure 29. the two-step command sequence for program/erase provides additional software protection. 4.2 ready/busy. the device has a ready/busy output that provides method of indicating the co mpletion of a page program, erase, copy-back and random read completion. the r/ b pin is normally high and goes to lo w when the device is busy (after a reset, read, program, erase operation). it returns to high wh en the internal controller ha s finished the operation. the pin is an open-drain driver thereby allowing two or more r/ b outputs to be or-tied. because pull-up resistor value is related to tr(r/ b ) and current drain during busy (ibusy), an appropriate value can be obtained with the following reference chart (fig 29). it s value can be determined by the following guidance. http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 16 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash parameter symbol min typ max unit valid block number n vb 3996 4096 blocks table 6: valid blocks number note: 1. the 1st block is guaranteed to be a valid block at the time of shipment. 2. this number of valid blocks is based on single plane op erations and may be little lower on two plane operations. symbol parameter value unit t a ambient operating temperature (commercial temperature range) 0 to 70 ambient operating temperature (industrial temperature range) -40 to 85 t bias temperature under bias -50 to 125 t stg storage temperature -65 to 150 v vio (2) input or output voltage -0.6 to 4.6 v vcc supply voltage -0.6 to 4.6 v table 7: absolute maximum ratings note: 1. except for the rating ?operating temperature rang e?, stresses above those listed in the table ?absolute maximum ratings? may cause permanent damage to th e device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sectio ns of this specification is not implied. exposure to absolute maximum rating co nditions for extended periods may affect device reliability. refer also to the hynix sure program and other relevant quality documents. 2. minimum voltage may undershoot to -2v during transition and for less than 20ns during transitions. http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 17 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash $''5(66 5(*,67(5 &2817(5 352*5$0 (5$6( &21752//(5 +9*(1(5$7,21 &200$1' ,17(5)$&( /2*,& &200$1' 5(*,67(5 '$7$ 5(*,67(5 ,2 5( %8))(56 <'(&2'(5 3$*(%8))(5 ; ' ( & 2 ' ( 5 0elw0elw 1$1')odvk 0(025<$55$< :3 &( :( &/( $/( $a$ figure 5: block diagram http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 18 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash parameter symbol test conditions 3.3volt unit min typ max operating current read i cc1 t rc =25ns ce =v il , i out =0ma - 15 30 ma program i cc2 - - 15 30 ma erase i cc3 - - 15 30 ma stand-by current (ttl) i cc4 ce =v ih , wp =0v/vcc - 1 ma stand-by current (cmos) i cc5 ce =vcc-0.2, wp =0v/vcc - 10 50 ua input leakage current i li v in= 0 to vcc (max) - - 10 ua output leakage current i lo v out =0 to vcc (max) - - 10 ua input high voltage v ih - 0.8xvcc - vcc+0.3 v input low voltage v il - -0.3 - 0.2xvcc v output high voltage level v oh i oh =-400ua 2.4 - - v output low voltage level v ol i ol =2.1ma - - 0.4 v output low current (r/ b ) i ol (r/ b ) v ol =0.4v 8 10 - ma table 8: dc and operating characteristics parameter value 3.3volt input pulse levels 0v to vcc input rise and fall times 5ns input and output timing levels vcc/2 output load (2.7v - 3.6v) 1 ttl gate and cl=50pf table 9: ac conditions http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 19 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash item symbol test condition min max unit input / output capacitance c i/o v il =0v - 10 pf input capacitance c in v in =0v - 10 pf table 1 0: pin capacitance (ta=25c, f=1.0mhz) parameter symbol min typ max unit program time / multi-plane program time t prog - 800 2000 us dummy busy time for two plane program t dbsy - 1 2 us number of partial program cycles in the same page nop - - 1 cycles block erase time / multi-plane block erase time t bers - 2.5 10 ms note : within a same block. program time (tprog) of page group a is faster than that of group b. the page group a and b are referred to table 22. table 1 1: program / erase characteristics http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 20 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash parameter symbol 3.3v unit min max cle setup time t cls 12 ns cle hold time t clh 5 ns ce setup time t cs 20 ns ce hold time t ch 5 ns we pulse width t wp 12 ns ale setup time t als 12 ns ale hold time t alh 5 ns data setup time t ds 12 ns data hold time t dh 5 ns write cycle time t wc 25 ns we high hold time t wh 10 ns data transfer from cell to register t r 60 us ale to re delay t ar 10 ns cle to re delay t clr 10 ns ready to re low t rr 20 ns re pulse width t rp 12 ns we high to busy t wb 100 ns read cycle time t rc 25 ns re access time t rea 20 ns re high to output high z t rhz 100 ns ce high to output high z t chz 50 ns ce high to output hold t coh 15 ns re high to output hold t rhoh 15 ns re low to output hold t rloh 5 ns re high hold time t reh 10 ns output high z to re low t ir 0 ns ce low to re low t cr 10 ns address to data loading time t adl 70 ns we high to re low t whr 80 ns re high to we low t rhw 100 ns device resetting time (read / program / erase) t rst 20/20/500 (1) us write protection time t ww (2) 100 ns table 1 2: ac timing characteristics note: 1. if reset command (ffh) is written at ready st ate, the device goes into busy for maximum 5us 2. program / erase enable operation : wp high to we high. program / erase disable operation : wp low to we high. http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 21 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash io pagae program block erase read coding 0 pass / fail pass / fail na pass: ?0? fail: ?1? 1 plane 0 pass/fail plane 0 pass/fail na plane 0, pass : ?0? fail : ?1? 2 plane 1 pass/fail plane 1 pass/fail na plane 1, pass : ?0? fail : ?1? 3 na na na - 4 na na na - 5 ready/busy ready/busy ready/busy busy: ?0? ready?: ?1? 6 ready/busy ready/busy ready/busy busy: ?0? ready?: ?1? 7 write protect write protect write protect protected: ?0? not protected: ?1? table 1 3: status register coding device identifier cycle description 1st manufacturer code 2nd device identifier 3rd internal chip number, cell type, etc. 4th page size, block size, spare size, organization 5th multi-plane information table 1 4: device identifier coding part number voltage bus width 1st cycle (manufacture code) 2nd cycle (device code) 3rd cycle 4th cycle 5th cycle H27UAG8T2M 3.3v x8 adh d5h 14h b6h 44h table 15: read id data table http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 22 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash description io7 io6 io5-4 io3 io2 io1-0 page size (without spare area) 1kb 2kb 4kb 8kb 0 0 0 1 1 0 1 1 spare area size (byte / 512byte) 8 16 0 1 serial access time 50ns 30ns 25ns reserved 0 0 1 1 0 1 0 1 block size (without spare area) 64k 128k 256k 512kb 0 0 0 1 1 0 1 1 organization x8 x16 0 1 table 17: 4th byte of devi ce identifier description description io7 io6 io5 io4 io3 io2 io1 io0 die / package 1 2 4 8 0 0 0 1 1 0 1 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 0 1 1 0 1 1 number of simultaneously programmed pages 1 2 4 8 0 0 0 1 1 0 1 1 interleave program between multiple chips not supported 0 1 write cache not supported 0 1 table 16: 3rd byte of device idendifier description http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 23 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash description io7 io6 io5 io4 io3 io2 io1 io0 plane number 1 2 4 8 0 0 0 1 1 0 1 1 plane size (w/o redundant area) 512mb 0 0 0 1gb 0 0 1 2gb 0 1 0 4gb 0 1 1 8gb 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved 0 0 0 table 18: 5rd byte of device idendifier description http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 24 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash figure 6: command latch cycle w&/ 6 w&6 w:3 &rppdqg &/( &( :( $/( ,2[ w'+ w'6 w$/6 w$/+ w&/+ w&+ w&/6 w&6 w:& w$/6 w$/6 w$/6 w$/6 w$/6 w$/+ w$/+ w$/+ w$/+ w$/+ w:& w:& w:& w:3 w:3 w:+ w:3 w:3 w:+ w:+ w:+ w'6 &ro$gg &/( &( :( $/( ,2[ &ro$gg 5rz$gg 5rz$gg 5rz$gg w'6 w'6 w'6 w'6 w'+ w'+ w'+ w'+ w'+ figure 7: address latch cycle http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 25 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash w:& w&/+ w&+ w:3 w:+ ',1 ',1 ',1ilqdo w:+ w'+ w'+ w'+ w'6 w'6 w'6 w:3 w:3 &/( $/( &( ,2[ :( w$/6 figure 8: input data latch cycle http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 26 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash w5& w53 w5(+ w5($ w&5 w5/2+ w55 w5($ w&+= w&2+ w5+= w5+2+ 'rxw 'rxw &( 5( ,2[ 5% 1rwhv7udqvlwlrqlvphdvxuhgdwp9iurpvwhdg\vwdwh yrowdjhzlwkordg 7klvsdudphwhulvvdpsohgdqgqrwwhvwhgw &+=w5+= w5/2+lvydolgzkhqiuhtxhqf\lvkljkhuwkdq0+] w5+2+vwduwvwrehydolgzkhqiuhtxhqf\lvorzhu wkdq0+] figure 10: sequential out cycle after read (edo type cle=l, we =h, ale=l) w5& &( 5( ,2[ 5% w5($ w55 'rxw 'rxw 'rxw 1rwhv7udqvlwlrqlvphdvxuhgdwp9iurpvwhdg\vwdwh yrowdjhzlwkordg 7klvsdudphwhulvvdpsohgdqgqrwwhvwhgw &+=w5+= w5+2+vwduwvwrehydolgzkhqiuhtxhqf\lvorzhu wkdq0+] w5($ w5+= w5+= w5($ w&+= w&2+ w5+2+ w5(+ figure 9: sequential out cycle after read (cle=l, we =h, ale=l) http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 27 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash figure 11: status read cycle w &/6 w &/5 w &/+ w &6 w &+ w :3 w :+5 w &5 w '6 w 5($ w &+= w &2+ w 5+= w 5+2+ k 6wdwxv2xwsxw w '+ w ,5 &( :( ,2 [ &/( 5( &/( $/( &( ,2[ :( 5( 5% w :& w &/5 w 55 k k &ro$gg &roxpq$gguhvv 5rz$gguhvv &ro$gg 5rz$gg 5rz$gg 5rz$gg %xv\ 'rxw1 'rxw1 'rxw0 w :% w $5 w 5 w 5& w 5+= figure 12: read1 operation (read one page) http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 28 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash w:% w$5 w&+= w&2+ w5& w5 w55 %xv\ k k 'rxw 1 'rxw 1 'rxw 1 &ro $gg &ro $gg 5rz $gg 5rz $gg 5rz $gg &roxpq$gguhvv 5rz$gguhvv &/( &( :( $/( 5( ,2[ 5% figure 13: read1 operation intercepted by ce http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 29 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash &/( $/( &( 5( 5% ,2[ :( w&/5 k &roxpq$gguhvv 5rz$gguhvv %xv\ k k (k 'rxw1 'rxw0 'rxw1 'rxw0 &ro$gg 5rz$gg 5rz$gg 5rz$gg &ro$gg &roxpq$gguhvv &ro$gg &ro$gg w5 w5& w:% w$5 w55 w:+5 w5($ w5+: figure 14: random data output http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 30 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash w:& w:& w:& w:& w&/5 w:+5 w5+: w5($ w5& w:+5 w5($ w5& w&/5 w:% w5 %xv\ k k &/( $/( &( 5( 5% ,2[ :( $a$)l[hg3/rz $)l[hg3/rz $a$)l[hg3/rz $a$9dolg $a$9dolg $a$)l[hg3/rz $a$)l[hg3/rz $)l[hg3/rz $a$)l[hg3/rz $a$)l[hg3/rz $a$)l[hg3/rz $)l[hg3+ljk $a$9dolg $a$9dolg $)l[hg3+ljk $a$9dolg k k (k k 5rz $gg 5rz $gg 5rz $gg 5rz $gg &ro $gg &ro $gg &ro $gg &ro $gg 'rxw 1 'rxw 1 'rxw 0 'rxw 0 5rz $gg 5rz $gg 5rz$gguhvv 5rz $gg 5rz $gg 5rz $gg 5rz$gguhvv &roxpq$gguhvv k 5rz $gg &ro $gg &ro $gg 5rz $gg 5rz $gg 5rz$gguhvv &roxpq$gguhvv &roxpq$gguhvv k (k &ro $gg &ro $gg &roxpq$gguhvv 5rz$gguhvv &/( $/( &( 5( 5% ,2[ :( figure 15: multi-plane page read operation with random data out http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 31 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash figure 16: page program operation &/( $/( &( 5( 5% ,2[ :( w:& k &ro $gg 6huldo'dwd ,qsxw&rppdqg &roxpq$gguhvv 127(6w$'/lvwkhwlphiurpwkh:(ulvlqjhgjhriilqdodggu hvvf\fohwrwkh:(ulvlqjhgjhriiluvwgdwdf\foh 5rz$gguhvv 5hdg6wdwxv &rppdqg 3urjudp &rppdqg ,2 6xffhvvixo3urjudp ,2 (uurulq3urjudp xswrp%\wh 6huldo,qsxw &ro $gg 5rz $gg 5rz $gg 5rz $gg 'lq 1 'lq 0 k k ,2 w:& w:% w352* w:+5 w:& w$'/ http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 32 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash &/( $ /( &( 5( 5% ,2[ :( w:& k 'lq 1 'lq 0 'lq - 'lq . k k k ,2 &ro$gg &ro$gg &ro$gg &ro$gg 5rz$gg 5rz$gg 5rz$gg w:& w:% w:+5 w352* 6huldo'dwd ,qsxw&rppdqg 5dqgrp'dwd ,qsxw&rppdqg &roxpq$gguhvv &roxpq$gguhvv 5rz$gguhvv 127(6w$'/lvwkhwlphiurpwkh:(ulvlqjhgjhriilqdodg guhvvf\fohwrwkh:(uvlqjhgjhriiluvwgdwdf\foh 6huldo,qsxw 6huldo,qsxw 3urjudp &rppdqg 5hdg6wdwxv &rppdqg w:& w$'/ w$'/ figure 17: random data in http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 33 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash figure 18: multiple plane page program $/( &/( &( 5( 5% ,2[ :( 5% ,2a ([7zr3odqh3djh3urjudp w:& k k k ,2 &ro$gg 5rz$gg %\wh'dwd &ro$gg 5rz$gg %\wh'dwd 1rwh $a$9dolg $a$)l[hg/rz? $)l[hg/rz? $a$)l[hg/rz? $a$9dolg $a$9dolg $)l[hg+ljk? $a$9dolg 1rwh$q\frppdqgehwzhhqkdqgklvsurklewhgh[fhswkd qg))+ w'%6< w352* 6huldo'dwd ,qsxw&rppdqg &roxpq$gguhvv 3djh5rz$gguhvv xswr%\wh'dwd 6huldo,qsxw 3urjudp &rppdqg 'xpp\ k k k k $gguhvv 'dwd,qsxw $gguhvv 'dwd,qsxw k 'lq 1 'lq 0 6huldo,qsxw 3urjudp &rppdqg 7uxh k 'lq 1 'lq 0 &ro$gg k &ro$gg 5rz$gg 5rz$gg 5rz$gg 5rz$gg &ro$gg &ro$gg 5rz$gg 5rz$gg w:% w:+5 w352* w:% w'%6< w'%6<xv7\s xv0d[ ,2 6xffhvvixo3urjudplqsodqh ,2 (uurulqsodqh ,2 6xffhvvixo3urjudplqsodqh ,2 (uurulqsodqh http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 34 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash figure 19: block erase op eration (erase one block) figure 20: multiple plane erase operation 5rz$gguhvv %orfn(udvh6hwxs&rppdqg %orfn(udvh6hwxs&rppdqg (udvh&rqil up&rppdqg 5hdg6wdwxv&rppdqg ,2 6xffhvvixo(udvhlqsodqh ,2 (uurulqsodqh ,2 6xffhvvixo(udvhlqsodqh ,2 (uurulqsodqh %xv\ 5rz$gguhvv ([$gguhvv5hvwulfwlrqiru7zr3odqh%orfn(udvh2shudwlrq $/( &/( &( 5( 5% ,2[ :( 5% ,2a w:& k k 5rz$gg 5rz$gg $a$)l[hg/rz? $)l[hg/rz? $a$)l[hg/rz? $a$)l[hg/rz? $)l[hg+ljk? $a$9dolg $gguhvv $gguhvv k k 'k k 'k k ,2 5rz$gg 5rz$gg 5rz$gg 5rz$gg 5rz$gg 5rz$gg w:& w:% w%(56 w%(56 w:+5 w:& &/( &( :( $/( 5( ,2 [ 5% w:% w%(56 %86< k ,2 5rz$gg 5rz$gg 5rz$gg k %orfn(udvh6hwxs&rppdqg (udvhfrqilup&rppdqg 5hdg6wdwxv &rppdqg ,2 6xffhvvixo(udvh ,2 (uurulq(udvh %orfn$gguhvv 'k http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 35 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash &( w:& w:% w5 &rodgg 5rzdgg &rodgg 5rzdgg 1rwh&rs\edfnsurjudprshudwlrqlvdoorzhgrqo\zlwklqwkhv dphsodqh k k ,2[ dgguhvv k k k 5hdgfrppdqg &roxpqdgguhvv &roxpqdgguhvv 'dwd2xw sdjhurzdgguhvv &rs\edfn 3urjudp frppdqg 3djhurzdgguhvv 5hdgfrqilup &rppdqg k k 'dwd 1 'dwd 0 k k ,2 &ro dgg &ro dgg 5rz dgg 5rz dgg 5rz dgg 5rz dgg 5rz dgg 5rz dgg &ro dgg &ro dgg k 'dwdrxw dgguhvv w352* w5 w552* :( 5( 5% ,2[ ,2 &/( $/( 5% figure 21: copy back program operation http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 36 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash &/( &( :( w:& w:% w5 w5& w$'/ w352* w:+5 w:% $ /( 5( k k k ,2 k k 'dwd 'dwd 'dwd 'dwd k 'dwd 'dwd %xv\ 127(6w$'/lvwkhwlphiurpwkh:(ulvlqjhgjhriilqdodgg uhvvf\fohwrwkh:(ulvlqjhgjhriiluvwgdwdf\foh &roxpq$gguhvv &roxpq$gguhvv 'dwd2xw 'dwd,q 5rz$gguhvv 5rz$gguhvv 5hdo6wdwxv&rppdqg %xv\ ,2 6xfhvvixo3urjudp ,2 (uurulq3urjudp &rs\%dfn'dwd ,qsxw&rppdqg &ro $gg 5rz $gg 5rz $gg 5rz $gg &ro $gg &ro $gg 5rz $gg 5rz $gg 5rz $gg &ro $gg &roxpq$gguhvv &ro $gg &ro $gg ,2[ 5% 5% w5 w352* ,2a k k &rodgg 5rzdgg &rodgg 5rzdgg &rodgg k k k ,2[ k dgguhvv dgguhvv dgguhvv 'dwdrxw 'dwd,q 'dwd,q figure 22: copy back program op eration with random data input http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 37 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash k 5rz$gg $a$)l[hg3/rz $)l[hg3/rz $a$)l[hg3/rz &ro$gg 5rz$gg &ro$gg $a$)l[hg3/rz $a$)l[hg3/rz $)l[hg3/rz $a$)l[hg3/rz $a$9dolg $a$9dolg $)l[hg3+ljk $a$9dolg 5rz$gg w5 k k $gguhvv&\foh $gguhvv&\foh k 5% ,2[ k (k 'dwd2xwsxw $gguhvv&\foh $gguhvv&\foh &ro$gg 5rz$gg &ro$gg $a$)l[hg3/rz $a$)l[hg3/rz $)l[hg3+ljk $a$)l[hg3/rz &ro$gg 5rz$gg 'hvwlqdwlrq$gguhvv $a$)l[hg3/rz $a$)l[hg3/rz $)l[hg3/rz $a$)l[hg3/rz &ro$gg 5rz$gg 'hvwlqdwlrq$gguhvv $a$)l[hg3/rz $a$9dolg $)l[hg3+ljk $a$9dolg $a$9dolg k k k $gg&\fohv k k k $gg&\fohv k (k 'dwd2xwsxw $gguhvv&\foh $gguhvv&\foh w'%6< w352* 5% ,2[ 5% ,2[ 5% ,2[ ,2 6xffhvvixo3urjudplqsodqh ,2 (uurulqsodqh ,2 6xffhvvixo3urjudplqsodqh ,2 (uurulqsodqh ,2 figure 23: multi-plane copyback program operation http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 38 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash k 5rz$gg $a$)l[hg3/rz $)l[hg3/rz $a$)l[hg3/rz &ro$gg 5rz$gg &ro$gg $a$)l[hg3/rz $a$)l[hg3/rz $)l[hg3/rz $a$)l[hg3/rz $a$9dolg $a$)l[hg3/rz $)l[hg3/rz $a$)l[hg3/rz $a$9dolg $a$9dolg $)l[hg3+ljk $a$9dolg 5rz$gg w5 k k $gguhvv&\foh $gguhvv&\foh k 5% ,2[ k (k 'dwd2xwsxw $gguhvv&\foh $gguhvv&\fohv $gguhvv&\foh &ro$gg 5rz$gg &ro$gg &ro$gg $a$)l[hg3/rz $a$)l[hg3/rz $)l[hg3+ljk $a$)l[hg3/rz &ro$gg 5rz$gg 'hvwlqdwlrq$gguhvv $a$9dolg $a$9dolg $)l[hg3+ljk $a$9dolg &ro$gg 5rz$gg 'hvwlqdwlrq$gguhvv $a$9dolg k k k (k 'dwd2xwsxw $gguhvv&\foh $gguhvv&\foh w'%6< w352* 5% ,2[ 5% ,2[ k k 'dwd 'dwd $gguhvv&\fohv $gguhvv&\fohv &ro$gg k k k 'dwd 'dwd $gguhvv&\fohv ,2[ ,2[ 5% 5% figure 24: multi-plane copy-back progra m operation with random data input note: 1. copy-back program operation is allowed only within the same memory plane. 2. any command between 11h and 81h is prohibited except 70h and ffh. http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 39 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash k &/( &( :( $/( 5( ,2[ k w5($ 5hdg,'&rppdqg $gguhvvf\foh 0dnhu&rgh 'hylfh&rgh $'k wk&\foh wk&\foh ug&\foh 'k %k k k w$5 figure 25: read id operation http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 40 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash ,ivhtxhqwldourzuhdghqdeohg &(pxvwehkhogorzgxulqjw5 &(grq?wfduh k k &/( &( 5( $/( 5% :( ,2[ 6wduw$gg&\foh 'dwd2xwsxwvhtxhqwldo w5 figure 27: read operation with ce don?t-care. system interface using ce don?t care to simplify system interface, ce may be deasserted during data loading or sequential data-reading as shown below. so, it is possible to connect nand flas h to a microprocessor. the only function that was removed from standard nand flash to make ce don?t care read operation was disabling of the automatic sequen tial read function. &(grq?wfduh k 6wduw$gg&\foh 'dwd,qsxw k 'dwd,qsxw &/( &( :( $/( ,2[ figure 26: program operation with ce don?t-care. http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 41 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash 9 9 9 9 9 xvpd[ ,qydolg 9 &( 9 ,/ 9 2shudwlrq pvpd[ ,+ && 9 ,/ :3 5% grq?w fduh grq?w fduh grq?w fduh figure 28: reset operation ))k w 567 :( $/( &/( 5( ,2 5% figure 29: power on and data protection timing vth = 2.5 volt for 3.3 volt supply devices http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 42 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash 5sydoxhjxlghqfh 5splq zkhuh,/lvwkhvxpriwkhlqsxwfxuuqwvridooghylfhvwlhgwr wkh5%slq 5spd[lvghwhuplqhge\pd[lpxpshuplvvleoholplwriwu #9ff 97d ?&& / s) )lj5syvwuwi 5syvlexv\ 9ff0d[9 2/ 0d[ 9 p$?, / , 2/ ?, / 5s lexv\ 5srkp lexv\ lexv\>$@ wuwi>v@ wi %xv\ 5hdg\ 9ff 9 2+ wu wi 9 2/ 9 2/ 99 2+ 9 9ff q p n n n n q p q p *1' 'hylfh rshqgudlqrxwsxw 5% figure 30: ready/busy pin electrical specifications http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 43 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash <hv <hv 1r 1r 67$57 %orfn$gguhvv %orfn 'dwd ))k" /dvw eorfn" (1' ,qfuhphqw %orfn$gguhvv 8sgdwh %dg%orfnwdeoh bad block management devices with bad blocks have the same quality level and th e same ac and dc characteristics as devices where all the blocks are valid. a bad block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. the devices are su pplied with all the locations inside valid blocks erased(ffh). the bad block information is written prior to shipping. any bl ock where the 1st byte in the spare area of the last and (last-2)th page (if the last page is bad) does not contain ffh is a bad block. the bad block information must be read before any erase is attempted as the bad block information may be erased. for the system to be able to recognize the bad blocks based on the original information it is recomm ended to create a bad block table following the flowchart shown in figure 32. the 1st block, which is placed on 00h block address is guaranteed to be a valid block. figure 31: bad block management flowchart note : 1. make sure that ffh at the column address 4096 of the last page and last - 2 th page. http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 44 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash 'dwd %xiihuphpru\riwkhfrqwuroohu %orfn$ %orfn% qsdjh ))k 'dwd ))k )dloxuh wk qsdjh wk bad block replacement over the lifetime of the device additional bad blocks may deve lop. in this case the block has to be replaced by copying the data to a valid block. these additional bad blocks can be identified as attemp ts to program or erase them will give errors in the status register. the failure of a page program operation does not affect the data in other page s in the same block, the block can be replaced by re-programming the current data and copying th e rest of the replaced block to an available valid block. refer to table 19 and figure 31 for the recommended proced ure to follow if an error occurs during an operation . operation recommended procedure erase block replacement program block replacement read ecc (with 4bit/528byte) table 19: block failure figure 32: bad block replacement note : 1. an error occurs on the block a during program or erase operation. 2. data in block a is copied to same location in block b which is valid block. 3. n th page of block a which is in controll er buffer memory is copied into n th page of block b 4. bad block table should be updated to prevent from erasing or programming block a http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 45 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash write protect operation the erase and program operations are automatically reset when wp goes low (tww = 100ns, min). the operations are enabled and disabled as follows (figure 33~36) k k w :: :( ,2[ :3 5% figure 33: enable programming :: w k k :( ,2[ :3 5% figure 34: disa ble programming k w 'k :: :( ,2[ :3 5% k w :: 'k :( ,2[ :3 5% figure 35: enable erasing figure 36: disable erasing http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 46 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash table 20: 48-tsop1 - 48-lead plastic thin small outline, 12 x 20mm, package mechanical data symbol millimeters min typ max a 1.200 a1 0.050 0.150 a2 0.980 1.030 b 0.170 0.250 c 0.100 0.200 cp 0.100 d 11.910 12.000 12.120 e 19.900 20.000 20.100 e1 18.300 18.400 18.500 e 0.500 l 0.500 0.680 alpha 0 5 figure 37: 48-tsop1 - 48-lead plastic thin small outline, 12 x 20mm, package outline ' $ ',( $ h % / . ( ( & &3 $ http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 47 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash symbol millimeters min typ max a 16.90 17.00 17.10 a1 13.00 a2 12.00 b 11.90 12.00 12.10 b1 10.00 b2 6.00 c1.00 c1 1.50 c2 2.00 d1.00 d1 1.00 e 0.65 cp1 0.65 0.70 0.75 cp2 0.95 1.00 1.05 figure 38: 52-ulga, 12 x 17mm, package outline (top view through package) % $ $ $ fs ( fs & & & % % '' 0 & $% 0 & $% table 21: 52-ulga, 12 x 17mm , package mechanical data http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 48 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash paired page address information note: when program operation is abnormally aborted (ex. power-down, reset), not only page data under program but also paired page data may be damaged. table 22: paired page address information paired page address paired page address group a group b group a group b ooh 04h 01h 05h 02h 08h 03h 09h 06h 0ch 07h 0dh 0ah 10h 0bh 11h 0eh 14h 0fh 15h 12h 18h 13h 19h 16h 1ch 17h 1dh 1ah 20h 1bh 21h 1eh 24h 1fh 25h 22h 28h 23h 29h 26h 2ch 27h 2dh 2ah 30h 2bh 31h 2eh 34h 2fh 35h 32h 38h 33h 39h 36h 3ch 37h 3dh 3ah 40h 3bh 41h 3eh 44h 3fh 45h 42h 48h 43h 49h 46h 4ch 47h 4dh 4ah 50h 4bh 51h 4eh 54h 4fh 55h 52h 58h 53h 59h 56h 5ch 57h 5dh 5ah 60h 5bh 61h 5eh 64h 5fh 65h 62h 68h 63h 69h 66h 6ch 67h 6dh 64h 70h 6bh 71h 6eh 74h 6fh 75h 72h 78h 73h 79h 76h 7ch 77h 7dh 7ah 7eh 7bh 7fh http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 49 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash k k k k k $gguhvv 'dwd,qsxw $gguhvv 'dwd,qsxw ,2a 5% w'%6< w352* 1rwh $a$9dolg $a$)l[hg3/rz $9dolg $a$)l[hg3/rz $a$9dolg $a$9dolg $0xvwehvdphzlwkwkhsuhylrxv $a$9dolg &ro$gg 5rz$gg xswr%\wh'dwd &ro$gg 5rz$gg xswr%\wh'dwd k k k k k 'dwd 'dwd k 'dwd2xwsxw $gg&\fohv $gg&\fohv $gg&\fohv $a$9dolg $a$)l[hg3/rz $0xvwehvdphzlwkwkhvrxufhsodqh $a$)l[hg3/rz $a$9dolg $a$9dolg $0xvwehvdphzlwkwkhvrxufhsodqh $a$9dolg &ro$gg 5rz$gg 6rxufh$gguhvv &ro$gg 5rz$gg &ro$gg 5rz$gg xswr%\wh'dwd xswr%\wh'dwd 'hvwlqdwlrq$gguhvv 'hvwlqdwlrq$gguhvv ,2[ 5% ,2[ 5% w'%6< w5 w352* the backward compatibility (2kbyte/page operation) 1. page program 2. copy back program note: any command between 11h and 80h is prohibited except 70h and ffh. note: 1. copy-back program operation is allowed only within the same memory plane. 2. any command between 11h and 85h is prohibited except 70h and ffh. http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 50 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash w5 w'%6< w352* k k k k 'dwd 'dwd k 'dwd2xwsxw $gg&\fohv $gg&\fohv $gg&\fohv &ro$gg 5rz$gg 6rxufh$gguhvv $a$9dolg $a$)l[hg3/rz $pxvwehvdphzlwkwkhvrxufhsodqh $a$)l[hg3/rz &ro$gg 5rz$gg &ro$gg 'hvwlqdwlrq$gguhvv xswr%\wh'dwd xswr%\wh'dwd k k k 'dwd 'dwd $gg&\fohv $gg&\fohv &ro$gg ,2[ 5% ,2[ 5% ,2[ 5% $a$9dolg $a$9dolg $0xvwehvdphzlwkwkhvruxfhsodqh $a$9dolg &ro$gg 5rz$gg 'hvwlqdwlrq$gguhvv 3. copy back program wi th random data input note: 1. copy-back program operation is allowe d only within the same memory plane. 2. any command between 11h and 85h is prohibited except 70h and ffh. http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 51 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash marking information - tsop1 / ulga marking example k o r h 2 7 u a g 8 t 2 m y w w x x - hynix - kor - H27UAG8T2Mxx-xx h: hynix 27: nand flash u: power supply ag: density 8 : bit organization t: classification 2: mode m: version x: package type x: package material x: bad block x: operating temperature - y: year (ex: 5=year 2005, 6= year 2006) - ww: work week (ex: 12= work week 12) - xx: process code note - capital letter - sm all letter : hynix symbol : origin country : u(2.7v~3.6v) : 16gbit : 8(x8) : m ulti level cell+ single die+large block : 2(1nce & 1r/nb; sequential row read disable) : 1st generation : t(48-tsop1), u(52-ulga) : blank(normal), r(lead & halogen free) : b(included bad block), s(1~5 bad block), p(all good block) : c(0 ~70 ), i(-40 ~85 ) : fixed item : non-fixed item : part number x x - x x http://www..net/ datasheet pdf - http://www..net/

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